POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP
DOI:
https://doi.org/10.59277/RRST-EE.2023.4.19Keywords:
Master slave flip-flop, Low power, Digital logic, Power area, Reduced number of transistorsAbstract
Flip-flops are the fundamental building blocks of the data path structure. It is a key component of digital circuits and systems. This work offers an exclusive master-slave flip-flop topology by ensuing clocked complementary metal oxide semiconductor (C2MOS) logic, minimizing the total device count and the count of clocked devices. Reducing the number of clocked devices reduces undesirable transient activity and reduces dynamic power dissipation. C2MOS logic connects static logic design with clock signal synchronization, resulting in power savings and increased speed. The area reduction is also attained by reducing the total number of devices. The proposed topology has been realized using only sixteen transistors, including six clocked devices, resulting in area compression. Layout-level simulation at 0.12 mm C2MOS design rule technology is used to investigate the performance. According to an investigation, the proposed topology achieves power savings ranging from 19.77 to 63.75 %, area compaction ranging from 22.03 to 66.30 %, power delay product (PDP) enhancement ranging from 18.56 to 53.91 %, energy-delay product (EDP) enhancement ranging from 5.61 % to 41.39 %, power energy product (PEP) enrichment ranging from 35.63 to 82.82 %, and power area product (PAP) enrichment ranging from 35.19 to 66.30 %.
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