• PANDIAN NAGARAJAN Department of ECE, SRMIST, Vadapalani Campus, Chennai, Tamil Nadu, 600026, India Author
  • THANDAPANI KAVITHA Department of ECE, Vel Tech, Chennai, Tamil Nadu 600062, India Author
  • NAGARAJAN ASHOK KUMAR Department of ECE, Sree Vidyanikethan Engineering College, Tirupati, Andhra Pradesh, 517102, India Author
  • ALEXANDER SHIRLY EDWARD Department of ECE, SRM institute of science and technology, Vadapalani Campus, Chennai – 600026, Tamilnadu, India Author




Master slave flip-flop, Low power, Digital logic, Power area, Reduced number of transistors


Flip-flops are the fundamental building blocks of the data path structure. It is a key component of digital circuits and systems. This work offers an exclusive master-slave flip-flop topology by ensuing clocked complementary metal oxide semiconductor (C2MOS) logic, minimizing the total device count and the count of clocked devices. Reducing the number of clocked devices reduces undesirable transient activity and reduces dynamic power dissipation. C2MOS logic connects static logic design with clock signal synchronization, resulting in power savings and increased speed. The area reduction is also attained by reducing the total number of devices. The proposed topology has been realized using only sixteen transistors, including six clocked devices, resulting in area compression. Layout-level simulation at 0.12 mm C2MOS design rule technology is used to investigate the performance. According to an investigation, the proposed topology achieves power savings ranging from 19.77 to 63.75 %, area compaction ranging from 22.03 to 66.30 %, power delay product (PDP) enhancement ranging from 18.56 to 53.91 %, energy-delay product (EDP) enhancement ranging from 5.61 % to 41.39 %, power energy product (PEP) enrichment ranging from 35.63 to 82.82 %, and power area product (PAP) enrichment ranging from 35.19 to 66.30 %.


(1) N.H. Weste, K. Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., (1985)

(2) P. Zhao, J. McNeely, W. Kuang, N. Wang, Z. Wang, Design of sequential elements for low power clocking system, IEEE Trans. VLSI Systems, 19, pp. 914–918 (2010).

(3) H. Kawaguchi, T. Sakurai, A reduced clock-swing flip-flop (RCSFF) for 63% power reduction, IEEE Jo. Solid-State Circuits, 33, pp. 807–811 (1998).

(4) P. Zhao, J. McNeely, W. Kuang, N. Wang, Z. Wang, Design of sequential elements for low power clocking system, IEEE Trans. VLSI, Systems, 19, pp. 914–918 (2010).

(5) J. Yuan, C. Svensson, High-speed CMOS circuit technique, IEEE Jour. Solid-State Circuits, 24, pp. 62–70 (1989).

(6) V. Stojanovic, V.G. Oklobdzija, Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems, IEEE Jour. Solid-Sate Circuits, 34, pp. 536–548 (1999).

(7) Y.T. Hwang, J.F. Lin, M.H. Sheu, Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme, IEEE Trans. VLSI Systems, 20, pp. 361–366 (2011).

(8) P. Zhao, J. McNeely, W. Kuang, N. Wang, Z. Wang, Design of sequential elements for low power clocking system, IEEE Trans. VLSI Systems, 19, pp. 914-918 (2010).

(9) T.A. Johnson, L.S. Kourtev, A single latch, high speed double-edge triggered flip-flop (DETFF), ICECS 2001. 8th IEEE Inter. Conf. on Electronics, Circs. and Sys, 1, pp. 189–192 (2001).

(10) C. Kim S. M. Kang, A low-swing clock double-edge triggered flip-flop, IEEE Jour. Solid-State Circuits, 37, pp. 648-652 (2002).

(11) H. Kawaguchi, T. Sakurai, A reduced clock-swing flip-flop (RCSFF) for 63 % power reduction, IEEE Jour. Solid-State Circuits, 33, pp. 807–811 (1998).

(12) P. Zhao, T.K. Darwish, M.A. Bayoumi, High-performance and low-power conditional discharge flip-flop, IEEE Trans. VLSI Systems, 12, pp. 477–484 (2004).

(13) N. Nedovic, V.G. Oklobdzija, Dual-edge triggered storage elements and clocking strategy for low-power systems, IEEE Trans. on VLSI Systems, 13, pp. 577–590 (2005).

(14) G. Gerosa, S. Gary, C. Dietz, D. Pham, K. Hoover, J. Alvarez, J. Kahle, A 2.2 W, 80 MHz superscalar risc microprocessor, IEEE Jour. Solid-State Circuits, 29, 1440–1454 (1994).

(15) H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, D. Draper, Flow-through latch and edge-triggered flip-flop hybrid elements, Proc. Inter. Solid-State Circuits Conf. Digest of Tech. Papers, ISSCC, San Francisco, CA, USA, pp. 138–139 (1996).

(16) A. Hirata, K. Nakanishi, M. Nozoe, A. Miyoshi, The cross charge-control flip-flop: A low-power and high-speed flip-flop suitable for mobile application SoCs, Digest of Technical Papers, Sympo., VLSI Circuits, Kyoto, Japan, pp. 306–307 (2005).

(17) F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, G. Yee, A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors, IEEE Jour. Solid-State Circuits, 340, pp. 712–716 (1999).

(18) C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, Y. Oowaki, Conditional data mapping flip-flops for low-power and high-performance systems, IEEE Trans. VLSI, Systems, 14, pp. 1379–1383 (2006).

(19) P. Nagarajan, R. Saravanan, P. Thirumurugan, Design of register element for low power clocking system. Information: An Inter. Interdiscip. Journal, 17, pp. 2903–2913 (2014).

(20) K. Absel, L. Manuel, R.K. Kavitha, Low-power dual dynamic node pulsed hybrid flip-flop featuring efficient embedded logic, IEEE Trans. VLSI systems, 21, pp. 1693–1704 (2012).

(21) I.A. Khan, M.T. Beg, Power efficient design of semi-dynamic master-slave single-edge-triggered flip-flop, International Journal on Electrical Engineering and Informatics, 11, 2, pp. 252–262 (2019).

(22) U. Chopra, A.K. Mishra, D. Vaithiyanathan, Performance analysis of non-identical master slave flip flops at 65 nm node, IJITEE, 9, 1S, pp. a10051191S19-2019 (2019).

(23) H. Wu, Y. Bai, X. Li, Y. Wang, Design of high-speed quaternary d flip-flop based on multiple-valued current-mode, Journal of Physics: Conference Series IOP Publishing, 1626, 1, p. 012067 (2020).

(24) G.R. Chowdary, T.R. Krishna, M.S. Pavan, M.U.V. Mahesh, P. Tejaswi, D.K. Reddy, Design and performance evaluation of D-flip-flop using various technology nodes, International Journal, 8, 5 (2020).

(25) H Jeong, T.W. Oh, S.C. Song, S.O. Jung, Sense-amplifier-based flip-flop with transition completion detection for low-voltage operation, IEEE Trans. VLSI Systems, 26, 4, pp. 609–620 (2018).

(26) J. Yuan, W. Tang, Z, Yu, S. Qiao, A low-power high-speed sense-amplifier-based flip-flop in 55 nm MTCMOS, Electronics, 9, 5, p. 802 (2020).

(27) G. M. Sung, A low power and high-speed conditional-precharge sense amplifier based flip-flop using single-ended latch, Int. Journal of Electrical and Computer Engineering, 16, 1, pp. 1–5 (2022).

(28) O.A. Shah, G. Nijhawan, I.A. Khan, Improved sense amplifier based flip flop design for low power and high data activity circuits, Journal of Applied Science and Engineering, 26, 7, pp. 1047–1053 (2022).

(29) R. Cantoro, M. Huch, T. Kilian, R. Martone, U. Schlichtmann, G. Squillero, Machine learning-based performance prediction of microcontrollers using speed monitors, IEEE International Test Conference (ITC), pp. 1–5 (2020).

(30) A. Boudouda, Power spectral density of dual randomized discontinuous pulse width modulation, Rev. Roum. Sci. Techn. – Électrotechn. Et Énerg., 68, 2, pp.132–138 (2023).

(31) L. Popescu, O. Craiu, Energy consumption analysis for an EV powertrain using three BLDC identical motors, Rev. Roum. Sci. Techn. – Électrotechn. Et Énerg., 68, 2, pp.152–157 (2023).






Électrotechnique et électroénergétique | Electrical and Power Engineering

How to Cite