GENERALIZATION OF THE TIME INFINITE IMPULSE RESPONSE DIGITAL FILTERS
DOI:
https://doi.org/10.59277/RRST-EE.2024.69.3.12Keywords:
Frequency locked loop (FLL), Digital filter, Phase locked loop (PLL), Digital circuit, Discrete linear systemAbstract
This work describes the generalization of a new kind of infinite impulse response (IIR) digital filter to filter the pulse signal periods. This kind of digital filter was designed using the previously designed frequency-locked loops (FLL), which are based on the time measurement and processing of both the input and output periods. FLL is a linear discrete system. Starting from the general form of difference equation of the IIR FLL digital filter of the third and fourth orders, the transfer functions and Z transform of the outputs are developed for the IIR FLL digital filter of any order. To demonstrate the capabilities and utility of the general equations, they were applied to design a suitable IIR digital filter using a fourth-order FLL. The filtering abilities and the analyses in the frequency domain of the designed low pass IIR digital filter are demonstrated using the theory of IIR digital filter and the corresponding MATLAB tools. Analyses of the fourth-order IIR FLL digital filter were also performed in the time domain using computer simulation in MATLAB.
References
(1) Dj.M. Perisic, New kind of IIR digital filters intended for pulse period filtering, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 69, 1, pp. 61–66 (2024).
(2) Dj.M. Perisic, Digital filters intended for pulse signal periods, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 67, 2, pp. 161–166 (2022).
(3) Dj.M. Perisic, Frequency locked loops of the third and higher order, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 66, 4, pp. 261–266 (2021).
(4) Dj.M. Perisic, A. Zoric, Ž. Gavric, N. Danilovic, Digital circuit for the averaging of the pulse periods, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 63, 3, pp. 300–305 (2018).
(5) Dj.M. Perisic, M. Bojovic, Application of time recursive processing for the development of the time/phase shifter, Engineering, Technology & Applied Science Research, 7, 3, 1582–1587 (2017).
(6) Dj.M. Perisic, M. Perisic, D. Mitic, M. Vasic, Time recursive frequency locked loop for the tracking applications, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 62, 2, pp. 195–203 (2015).
(7) Dj.M. Perisic, A. Zoric, M. Perisic, V. Arsenovic, Lj. Lazic, Recursive PLL based on the measurement and processing of time, Electronics and Electrical Engineering, 20, 5, pp. 33–36 (2014).
(8) Dj.M. Perisic, A. Zoric, M. Perisic, D. Mitic, Analysis and application of FLL based on the processing of the input and output period, Automatika, 57, 1, p. 230–238 (2016).
(9) Dj.M Perisic, M. Bojovic, Multipurpose time recursive PLL, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 61, 3, pp. 283–288 (2016).
(10) Dj.M Perisic, M. Perisic, S. Rankov, Phase shifter based on a recursive phase locked loop of the second order, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 59, 4, pp. 391–400 (2014).
(11) Dj. M. Perisic, A. Zoric, Dj. Babic, Dj. Perisic, Decoding and prediction of energy state in consumption control, Rev. Roum. Sci. Techn. – Electrotechn. et Energ., 58, 3, pp. 263–272 (2013).
(12) D. Jovcic, Phase locked loop system for FACTS, IEEE Transaction on Power System, 18, pp. 2185–2192 (2003).
(13) A.S.N. Mokhtar, B.B.I. Reaz, M. Maruffuzaman, M.A.M. Ali, Inverse Park transformation using cordic and -phase-locked loop, Rev. Roum. Sci. Techn. – Électrotechn. Et Énerg., 57, 4, pp. 422–431, (2012).
(14) C.C. Chung, An all-digital phase-locked loop for high speed clock generation, IEEE Journal of Solid-State Circuits, 38, 2, pp. 347–359, (2003).
(15) F. Amrane, A. Chaiba, B.E. Babes, S. Mekhilef, Design and implementation of high performance field oriented control for grid-connected doubly fed induction generator via hysteresis rotor current controller, Rev. Roum. Sci. Techn. – Électrotechn. Et Énerg., 61, 4, pp. 319–324 (2016).
(16) M. Büyük, M. İnci, M. Tümay, Performance comparison of voltage sag/swell detection methods implemented in custom power devices, Rev. Roum. Sci. Techn. – Électrotechn. Et Énerg., 62, 2, pp. 129–133 (2017).
(17) L. Joonsuk, B. Kim, A low noise fast-lock phase-locked loop with adaptive bandwidth control-solid-state circuit, IEEE Journal, 35, 8, pp. 1137–1145 (2000).
(18) D. Abramovitch, Phase-locked loops: a control centric tutorial, American Control Conference-2002, Proceedings of 2002, 1, pp. 1–15 (2002).
(19) R. Vich, Z Transform Theory and Application (Mathematics and Applications), Ed. Springer (1987-first edition).
(20) S.W. Smith, Digital Signal Processing (second edition), California Technical Publishing (1999).
(21) G. Bianchi, Phase-Locked Loop Synthesizer Simulation, Nc-Hill, Inc. New York, USA (2005).
(22) W.F. Egan, Phase-Lock Basics (second edition), John Wiley and Sons (2008).
(23) B.D. Talbot, Frequency Acquisition Techniques for PLL, Wiley-IEEE Press (2012).
(24) C.B. Fledderman, Introduction to Electrical and Computer Engineering, Prentis Hall (2002).
(25) M. Gardner, Phase lock techniques, Hoboken, Wiley-Interscience (2005).
(26) S. Winder, Analog and Digital Filter Design, Second edition, Elsevier Inc. (2002).
Downloads
Published
Issue
Section
License
Copyright (c) 2024 REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.