• DJURDJE PERIŠIĆ Faculty of Information Technologies, Slobomir P University, Str. Pavlovića put 76, 76300 Slobomir, Republic of Srpska, Bosnia and Herzegovina


Frequency locked loop, Digital filter, Phase-locked loop, Digital circuit, Discrete linear system


This work describes a new kind of FIR digital filter intended for the filtering of the pulse signal periods. This kind of digital filter was designed using the frequency locked loops (FLL), which are based on the time measurement and processing of the input periods only. FLL is a linear discrete system. Starting from the general form of differential equation of FLL, the transfer functions of FLL and Z transform of the FLL outputs are developed for FLL of any order. The main part of the article is devoted to describing how to design the appropriate FIR digital filter using an FLL of any order. Although the FIR digital filters and FLLs are different systems, for this purpose the theory of FIR digital filter and the corresponding MATLAB tools are used. Filtering abilities of the fifth-order FLL are demonstrated. The mathematical analyzes were performed using the Z transform approach. Analysis of FLL of the fifth-order was performed in the time and frequency domain. Computer simulation of FLL of the fifth-order is made in the time domain to enable precise insight into its properties.


(1) Dj. M Perisic, "Frequency locked loops of the third and higher-order", Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., (In revision).

(2) Dj. M. Perisic, V. Petrovic, B. Kovacevic "Frequency locked loop based on the time nonrecursive processing", Engineering, Technology & Applied Science Research, 8, 5, pp. 3450-3455 (2018).

(3) Dj. M. Perisic, A. Zoric, Ž. Gavric, N. Danilovic "Digital circuit for the averaging of the pulse periods", Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 63, 3, pp. 300-305 (2018).

(4) Dj. M. Perisic, M. Bojovic, "Application of time recursive processing for the development of the time/phase shifter", Engineering, Technology & Applied Science Research, 7, 3, pp. 1582-1587, (2017).

(5) Dj. M. Perisic, M. Perisic, D. Mitic, M. Vasic "Time recursive frequency locked loop for the tracking applications", Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 62, 2, pp. 195-203, Bucarest, (2015).

(6) Dj. M. Perisic, A. Zoric, M. Perisic, V. Arsenovic, Lj. Lazic, Recursive PLL based on the measurement and processing of time, Electronics and Electrical Engineering, 20, 5, pp. 33-36, (2014).

(7) Dj. M. Perisic, A. Zoric, M. Perisic, D. Mitic, Analysis and application of FLL based on the processing of the input and output periods. Automatika, 57, 1, pp. 230–238 (2016).

(8) Dj.M Perisic, M. Bojovic, Multipurpose time recursive PLL, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 61, 3, pp. 283-288, Bucarest, (2016).

(9) Dj.M Perisic, M. Perisic, S. Rankov, Phase shifter based on a recursive phase locked loop of the second order, Rev. Roum. Sci. Techn. – Électrotechn. et Énerg., 59, 4, pp. 391–400, (2014).

(10) Dj.M. Perisic, A. Zoric, Dj. Babic, Dj.Dj. Perisic, Decoding and prediction of energy state in consumption control, Rev. Roum. Sci. Techn. – Electrotechn. et Energ., 58, 3, pp. 263–272, Bucarest, (2013).

(11) D. Jovcic, Phase locked loop system for FACTS, IEEE Transaction on Power System, 18, pp. 2185-2192 (2003).

(12) A.S. N. Mokhtar, B.B.I. Reaz, M. Maruffuzaman, M.A.M. Ali, Inverse Park transformation using cordic and phase-locked loop, Rev. Roum. Sci.Techn.-Electrotechn. et Energy., 57, 4, pp. 422-431 (2012).

(13) C. C. Chung, An all-digital phase-locked loop for high-speed clock generation, IEEE Journal of Solid-State Circuits, 38, 2, pp. 347-359 (2003).

(14) F. Amrane, A. Chaiba, B.E. Babes, S. Mekhilef, Design and implementation of high-performance field-oriented control for grid-connected doubly fed induction generator via hysteresis rotor current controller, Rev. Roum. Sci. Techn. Et Energy., 61, 4, pp. 319–324 (2016).

(15) M. Büyük, M. İnci, M. Tümay, Performance comparison of voltage sag/swell detection methods implemented in custom power devices, Rev. Roum. Sci. Techn. – Electrotechn. et Energ., 62, 2, pp. 129–133 (2017).

(16) L. Joonsuk, B. Kim, A low noise fast-lock phase-locked loop with adaptive bandwidth control-Solid-State Circuit, IEEE Journal, 35, 8, pp. 1137-1145 (2000).

(17) D. Abramovitch, Phase-locked loops: a control centric tutorial, American Control Conference-2002, Proceedings of 2002, 1, pp. 1-15 (2002).

(18) R. Vich, Z Transform Theory and Application (Mathematics and Applications), Ed. Springer (1987-first edition).

(19) G. Bianchi, Phase-Locked Loop Synthesizer Simulation, Nc-Hill, Inc. New York, US, (2005).

(20) B.D. Talbot, Frequency Acquisition Techniques for PLL, Wiley-IEEE Press (2012).

(21) C.B. Fledderman, Introduction to Electrical and Computer Engineering, Prentis Hall, (2002).

(22) M. Gardner, Phase lock techniques, Hoboken, Wiley-Interscience (2005).

(23) S. Winder, Analog and Digital Filter Design (second edition), © 2002 Elsevier Inc. (2002).






Électronique et transmission de l’information / Electronics & IT