ANALYSIS OF THE TIME-FREQUENCY LOCKED LOOPS USING TABLES – PART 2
DOI:
https://doi.org/10.59277/RRST-EE.2026.3.12Keywords:
Time-Frequency locked loop, Tracking; Digital circuit, Discrete linear system, Time-digital filterAbstract
This article describes the universal tabular methods for the Time-Frequency Locked Loop (TFLL) analysis. TFLLs are open-loop linear discrete systems that process the input signal over time periods. Using tables, we can determine either the complete equations of the Z-transform from various phases of mathematical development or the expressions that represent the results of complex, lengthy mathematical analysis. The tabular method was developed for the TFLLs of lower order and extended to TFLL of the fifth order. It was shown how to extend the table to TFLLn of any order. The usage of the table is demonstrated in the tracking and prediction applications of the second- and third-order TFLL. However, the table approach can also be used for all other kinds of linear discrete systems. Mathematical analyses were performed by the Z-transform of the difference equations describing the system. The corresponding MATLAB application software for FIR digital filters was used for the frequency-domain analyses.
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