REAL-TIME VEDIC MATHEMATICS BASED MEMORYLESS ARITHMETIC CIRCUITS VERIFICATION TECHNIQUE (REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE, 2025)
This paper proposes a new method for verifying arithmetic circuit operations based on the Vedic mathematics Sutra (formulae) “Gunita Samuccaya”. According to this sutra, our proposed method verifies arithmetic operations, e.g., c = a + b, by checking whether the sum of 'a' and 'b' digits equals the sum of digits of 'c' for correct computation. In contrast to built-in self-test (BIST) schemes, our approach is simpler, eliminating traditional test pattern generators and output analyzers while achieving 100% fault coverage for simple arithmetic operations. Our system, designed in Verilog hardware description language (HDL), is real-time, memoryless, and scalable. This proposed testing method revolutionizes arithmetic circuit verification, guaranteeing the integrity of intricate digital systems where mathematical precision is vital.
Keywords: Testing; Formal verification; Vedic mathematics; Arithmetic circuits; Test vectors; Very large scale integration (VLSI)