(untitled) (REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE, 2023)
The foremost objective of this work is to propose a fault-tolerant (FT) asymmetrical 21-level inverter with minimal power semiconductor switches and voltage sources. The topology of the proposed inverter is to produce high voltage levels with low harmonic content and minimize electromagnetic interference (EMI) in the system. Meanwhile, the novelty has been proved by a detailed comparison between the suggested multilevel inverter (MLI) and recently introduced topologies using several components such as switches, capacitors, sources, gate driving circuits, total standing voltage (TSV), component count per level and cost function. Additionally, the flexible circuit connection between sources, switches, and loads provides the alternative configuration for 21-level MLI to operate as a 9-level and 7-level MLI topology, ensuring FT capability during the failure of specific sources and switches. The nearest voltage level (NVL) algorithm technique produces gate driver signals for the switches, which generate high-quality waveform compared to other pulse width modulation (PWM) techniques. A simulation model is designed to support the simulation results using MATLAB/Simulink software and hardware implementation. The results are analyzed under different combinations of linear and nonlinear loads. In both simulation and experiment, the evaluated parameter values show good performance concerning other structures, and total harmonic distortion (THD) is less than 5 % as per IEE519 standards.